1. Technical Field
This disclosure relates to semiconductor testing and more particularly, to bit map compression with the capability for fail signature analysis for bit fail maps for semiconductor memories. The present invention may also be employed for general data compression in other fields.
2. Description of the Related Art
Semiconductor testing is needed for quality control of both manufacturing processes and the product itself. Testing provides an understanding of the type of defects and their location on a semiconductor wafer. Memories give fail locations during electrical tests, since each memory cell has an X, Y coordinate on the chip. Defects in the memory array will cause these memory cells to fail, which are then detected by the electrical tests.
Actual defects are determined using electrical tests after the chips are fabricated. After electrical testing, some chips with defects may be salvaged by employing redundancies. Prior to employing the redundancies pre-fuse yield data may be obtained to determine if redundancies are needed or would improve yield.
A full bit map technique or a fail vector technique may be used to generate locations of failures. A full bit map approach generates a huge amount of data for example, 64 Mbit, 256 MBit, etc. depending on the chip size, which are difficult to store and to process. Signature analysis is slow due to the large amount of data to process. A fail vector memory generates an address for every fail during testing. A cell failing three read operations in a pattern is stored as three fail vectors, for example. Each fail vector has the address of the failure and the input/output pin (DQ) information saved. For example, in a 64M memory, 26 bits are needed for the address of the failure.
A compressed bit fail maps for the fail vector memory approach needs 64*32+3*16*16=2816 bit storage space for a 64 Mbit chip with 3 failures. This is equivalent to 2816/26=108 fail vectors. A failing DQ, a failing bitline (BL) or wordline (WL) will cause overflow of the fail vector memory due to the number of fail vectors and the enormous amount of memory needed to store the vectors. This also makes exact fail signature determination very difficult. Consequently other fail information is lost.
Therefore, a need exists for a bit map compression method and apparatus for reducing the amount of storage capacity needed for storing failure information for semiconductor memory devices. A further need exists for providing failure analysis capability for the bit map compression method and apparatus.
A method for providing a compressed bit fail map in accordance with the present invention includes testing a semiconductor device to determine failed devices, transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.
In alternate methods, the step of providing failure classification may include the step of determining a resolution of the fail area dimension for each failure type such that the resolution is sufficient to display a given number of fail types. The step of providing failure classification by designating shapes and dimensions of fail areas may include designating rectangular areas in a display to represent a plurality of different fail types in a memory array. The step of transferring failure information to display a compressed bit map may include logically combining physical addresses of failures to determine a display address in which to map the failure on the compressed bit map. The method may include the steps of determining a physical address which identifies a location of a first cell failure wherein the fail type designates the size and the dimension of remaining cell failures associated with the first cell failure, and eliminating other address information for the remaining cell failures to reduce memory storage. The step of providing failure classification by designating shapes and dimensions of fail areas may include the step of generating a plurality of compressed bit maps by employing scaling parameters to adjust the resolution of the maps, and designating additional addresses for the compressed bit maps to differentiate failures in overlapping areas of the compressed bit fail map to identify a physical address of the fail type. The method may include the step of employing a probability calculation to determine a physical address of a failure. The method may include the steps of calculating redundancies by generating a row map and a column map to identify failures in rows and columns, respectively, of a memory array, replacing the failed rows and columns, compressing the row map and the column map to generate a subarray map to identify memory cell failures in the memory array and replacing the memory cell failures. The step of transferring failure information to display a compressed bit map may include translating physical addresses of failures to determine display addresses in which to map the failure on the compressed bit map. The translating may be performed by employing a switch network, a lookup table or an equation.
Another method for generating a compressed bit fail map includes the steps of providing a semiconductor memory device under test, determining physical addresses of failed memory cells in a memory array of the device under test, the physical addresses being determined by generating a test sequence and running the test sequence a plurality of times to generate a plurality of compressed bit fail maps. The compressed bit fail maps are generated by: transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device and providing failure classification by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.
In alternate methods, the test sequence may be altered by a scrambling device and the step of generating a different scramble setup for generating each of the plurality of compressed bit fail maps may be included. The method may include step of generating the test sequence by a pattern generator.
The above methods may be implemented using a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating a compressed bit fail map.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.